-- Vhdl test bench created from schematic C:\xilinks\Pokus2\schema.sch - Wed Mar 31 14:11:38 2010
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY schema_schema_sch_tb IS
END schema_schema_sch_tb;
ARCHITECTURE behavioral OF schema_schema_sch_tb IS 

   COMPONENT schema
   PORT( clk_1Hz	:	IN	STD_LOGIC; 
          ld_1	:	OUT	STD_LOGIC; 
          ld_2	:	OUT	STD_LOGIC; 
          ld_0	:	OUT	STD_LOGIC; 
          btn_0	:	IN	STD_LOGIC; 
			 btn_1	:	IN	STD_LOGIC; 
			 sw_0	:	IN	STD_LOGIC; 
			 sw_1	:	IN	STD_LOGIC; 
			 sw_2	:	IN	STD_LOGIC;
		    sw_3	:	IN	STD_LOGIC; 			 
          ld_6	:	OUT	STD_LOGIC; 
          ld_7	:	OUT	STD_LOGIC);
   END COMPONENT;

   SIGNAL clk_1Hz	:	STD_LOGIC;
   SIGNAL ld_1	:	STD_LOGIC;
   SIGNAL ld_2	:	STD_LOGIC;
   SIGNAL ld_0	:	STD_LOGIC;
   SIGNAL btn_0	:	STD_LOGIC;
	SIGNAL btn_1	:	STD_LOGIC;
	SIGNAL sw_0	:	STD_LOGIC;
	SIGNAL sw_1	:	STD_LOGIC;
	SIGNAL sw_2	:	STD_LOGIC;
	SIGNAL sw_3	:	STD_LOGIC;	
   SIGNAL ld_6	:	STD_LOGIC;
   SIGNAL ld_7	:	STD_LOGIC;

BEGIN

   UUT: schema PORT MAP(
		clk_1Hz => clk_1Hz, 
		ld_1 => ld_1, 
		ld_2 => ld_2, 
		ld_0 => ld_0, 
		btn_0 => btn_0, 
		btn_1 => btn_1, 
		sw_0 => sw_0, 
		sw_1 => sw_1, 
		sw_2 => sw_2, 
		sw_3 => sw_3, 
		ld_6 => ld_6, 
		ld_7 => ld_7
   );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
		btn_0 <= '0';
		btn_1 <= '0';
		
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
		clk_1Hz <= '1';
		wait for 20ns;
		clk_1Hz <= '0';
		wait for 20ns;
	
      WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;
